1. Field of the Invention
The present invention relates to a logic circuit and a semiconductor integrated circuit including the logic circuit, and more particularly, to a semiconductor device adapted to a low-power operation.
2. Description of Related Art
Miniaturization of a manufacturing process of a semiconductor integrated circuit has recently been advancing. Therefore, withstand voltage of an MOS transistor forming the semiconductor integrated circuit such as CMOS LSI is decreased and operating voltage of the MOS transistor needs to be decreased. As the operating voltage decreases, operation speed of the MOS transistor is reduced. In order to prevent the operation speed from being reduced, threshold value voltage of the MOS transistor needs to be decreased.
However, when the threshold value voltage is decreased (for example about 0.4V or less), the transistor cannot be completely turned off, and subthreshold leak current flows between a drain and a source. This leak current causes a serious problem in the semiconductor integrated circuit such as LSI formed by a plurality of MOS transistors. This is because a pass-through current due to leak current of the transistor is generated even when the circuit in the semiconductor integrated circuit is logically in a disable state. There are caused significant problems such as increase of power consumption due to the pass-through current, increase of load to a power source, decrease of energy consumption efficiency, and increase of heat generation. These problems are obvious in the transistor of low-threshold voltage where high-speed operation is required. The leak current places severe limitation in realizing not only a circuit where low-power operation is required but also a circuit requiring high-speed operation. Further, the above-mentioned problems can further be serious since the subthreshold leak current exponentially increases in high-temperature operation of the semiconductor integrated circuit.
In order to overcome these problems, various techniques for reducing leak current in the semiconductor integrated circuit are suggested. One of the techniques is disclosed in Japanese Unexamined Patent Application Publication No. 2003-224465. In this Japanese Unexamined Patent Application Publication No. 2003-224465, a technique for intercepting leak current of the transistor having low-threshold voltage by the transistor having high-threshold voltage is disclosed.
Further, in Japanese Unexamined Patent Application Publication No. 5-22110, a technique for decreasing the pass-through current between an N-channel transistor and a P-channel transistor is disclosed.
According to the prior art as in Japanese Unexamined Patent Application Publication No. 2003-224465, the N-channel transistor or the P-channel transistor needs to be connected to ground or power source through the transistor having high-threshold voltage. This increases combined resistance when the transistor is turned on and increases output transition delay in normal operation, which reduces circuit operation speed.
Although the pass-through current in operation is decreased in the circuit configuration of the prior art such as Japanese Unexamined Patent Application Publication No. 5-22110, the leak current of the output transistor in an non-operating state is not considered.
Accordingly, it is desired to reduce the leak current without degrading circuit operation in the semiconductor integrated circuit such as CMOS LSI.